`include "defines.v"

module pc(
  input wire                clk,
  input wire                rst,
  input wire                flush,
  input wire   [`I_BUS]     new_pc,

  input wire   [`RAM_BUS]   inst_64,     
  
  output reg   [`I_BUS]     pc,
  output reg   [31 : 0]     inst,
  output wire               inst_ena
  
);

parameter PC_START_RESET = `PC_START - 4;


// fetch an instruction
always@( posedge clk )
begin
    if( rst == `RST )
        pc <= PC_START_RESET ;
    else if(flush)
        pc <= new_pc;
    else
        pc <= pc + 4;
end
/*
always@( posedge clk )
begin
    if( rst == `RST )
        inst <= 32'b0 ;
    else
        inst <= pc[2] ? inst_64[63 : 32] : inst_64[31 : 0];
end
*/
/*
// Access memory
reg [63:0] rdata;

RAMHelper RAMHelper(
  .clk              (clk),
  .en               (1),
  .rIdx             ((pc - `PC_START) >> 3),
  .rdata            (rdata),
  .wIdx             (0),
  .wdata            (0),
  .wmask            (0),
  .wen              (0)
);
*/
assign inst = pc[2] ? inst_64[63 : 32] : inst_64[31 : 0];
assign inst_ena  = ( rst == 1'b1 ) ? 0 : 1;

endmodule
